The Gemini Core Library or libgcore is a low-level API for the Gemini Tester. With it you can work with all the Gemini-specific file types. It also provides a simple API to the Gcore Linux driver.


Leda is a test pattern Dots compiler written in C that utilizes libgcore. It compiles a domain specific language called Dots, that was designed for easily creating test patterns.

(closed source)

VecOS is a specially designed board support package (BSP) for the Gemini Tester. It includes a custom Linux kernel, bootloader, config files, startup scripts, compiled binaries, libgcore, a Python website and more. It's designed to run on the Gemini Tester and orchestrate the entire system.

Gcore Driver

Gcore is a Linux kernel driver that provides an ioctl interface, that can be called from userspace, allowing for communication to, and configuration of, the Subcore IP block. The device driver can also be opened with mmap, and provides a way to DMA data to and from userland and beyond. It uses the Linux DMA Engine API to initiate DMA transactions from the Zynq FPGA to Agent.

Subcore IP
(closed source)

Subcore is a SystemVerilog IP block for the Gemini Tester that interfaces with the Linux Gcore Driver. It's purpose is to configure the Artix FPGAs, DMA data to and from RAM, communicate with the Agent IP block on the Artix FPGAs, and other administrative functions.

Agent IP
(closed source)

Agent is a SystemVerilog IP block for the Gemini Tester that interfaces with the Gemini VPU. It's purpose is to supervise and control the vector processing units, provide real-time statistics, and DMA data to and from local RAM.

Gemini VPU IP
(closed source)

The GVPU is the heart of the Gemini Tester. It's a vector processing unit IP core, written in SystemVerilog, that reads and executes 1024-bit test vector instruction words from Artix RAM, at high speed, and in sync with other GVPUs. It drives and expects vectors on the Gemini Test Bus, and reports the pass/fail status and the failing cycle number to Agent. It has a simple instruction set and architecture that's designed for extremely low-latency vector execution, without ever stalling the buffers.


Fastroute is an A* graph router written in C. It can route an arbitrary graph with nodes and weighted arcs. It was used in an FPGA router project that I was working on at Xilinx. I mainly wrote Fastroute for fun as a way to improve my C coding skills.